Forming a plurality of integrated circuit chips in a semiconductor wafer generally involves a plurality of processing steps. Because of the complex manufacturing process, defects are inevitably found on some chips. Therefore, before the steps of wafer dicing and separation of the integrated circuit chips from the semiconductor wafer, it is necessary to test the integrated circuit chips to determine whether the integrated circuit chips are defective or not.
Generally speaking, to test an integrated circuit (IC) chip, the IC chip is engaged and probed by a probe needle assembly, where electric signals relating to the electric properties of the IC chip is transmitted to a tester for analysis so as to determine whether the integrated circuit chip is defective or not. Conventionally, the probe needle assembly is composed of a plurality probe needles that are arranged in an array for allowing the plural probe needles to engage respectively to their corresponding electric pads of the IC chip and thus enabling testing signals from the tester to be transmitted precisely to the IC chip.
Please refer to FIG. 1, which is a schematic diagram showing a conventional electrical property test device. As shown in FIG. 1, the electrical property test device 1 includes a circuit board 10, a converting plate 11, and a probe assembly 12. The circuit board 10 has a plurality of first conductors 100 disposed thereon for allowing the plural first conductors 100 to connect electrically to a plurality of second conductors 110 that are disposed on a top surface of the converting plate 11. In addition, there are a plurality of third conductors 111 disposed on a bottom surface of the converting plate 11 at positions connected electrically and respectively to a plurality of probe needles 120 of the probe assembly 12. Thereby, through the electrical connection between the probe needles 120 of the probe assembly 12 and the electric pads 131 formed in a IC chip 130 of a wafer 13, electrical signals relating to the electrical properties of the IC chip 130 can be transmitted to the circuit board 10 through the converting plate 11, whereas the signals are further being transmitted through the conductive lines 101 formed on the circuit board 10 to a tester for subsequent analysis.
In the current market, the converting plate 11 is generally manufactured and assembled by a semiconductor package process, and due to cost considerations, there is a growing trend of providing thinner converting plate 11. Moreover, when the electrical property test device 1 is used for conducting a probing test, the probes 120 of the probe assembly 12 should be engaged with the electric pads 131 of the device under test 130 (herein referred to as the DUT thereafter), so that it is required to have a great amount probes 120 to be arranged and distributed within an area capable of enclosing the electric pads 131 of the DUT 130. Nevertheless, at the time when the probes 120 are enabled to engage electrically to the converting plate 11, the DUT 130 will exert a reaction force to the probes 120, so as to make the probes 120 apply the force on the converting plate 11. Consequently, since the converting plate 11 is a thin plate and all the probes 12 are distributed in a small area on the converting plate 11 that is conforming to the distribution of the electric pads 131 of the DUT 130, the converting plate 11 can easily be deformed or even cracked by the force, causing a severe adverse affect upon the subsequent analysis.